Field of the Invention
The invention relates to a semiconductor memory, particularly to a circuit arrangement in a synchronous burst nonvolatile semiconductor memory for reading out data.
A synchronous ROM that is a synchronous burst nonvolatile semiconductor memory comprises a memory array having a plurality of memory cells which are arranged in a matrix, a first latch circuit for storing a plurality of data which is read out asynchronously from a part of the memory cell array and outputting each data sequentially which data is stored in each address indicated by an address signal in response to the address signal which is supplied sequentially, an address generation control circuit for outputting a continuous address signal (hereinafter referred to as a burst address signal) to the first latch circuit in response to a burst control signal and a clock signal so as to output data sequentially to the first latch circuit, and a second latch circuit for receiving an output signal from the first latch circuit and outputting the output signal in synchronization with an internal clock signal.
The address generation control circuit has an address counter and a decoder circuit. The address counter latches therein an address signal BA (first address signal of the burst address signal) (hereinafter referred to as address signal BA) from a column latch circuit when receiving a burst control signal BS of H level from a timing control circuit in a state where the address signal BA that is an external binary address data is supplied thereto from the column latch circuit. The address generation control circuit outputs the latched address signal BA to the decoder circuit. The decoder circuit decodes a signal from the address counter and outputs the decoded signal to the first latch circuit. The address counter continuously generates the burst address signal in synchronization with the internal clock signal while a burst control signal BURST from the burst control circuit is high in level (hereinafter simply referred to as H level) after outputting the address signal BA. The address counter outputs the generated burst address signal sequentially to the first latch circuit.
Since the timing control circuit in the synchronous ROM operates in synchronization with the internal clock signal, the burst control signal BS outputted therefrom has a delay from the internal clock signal.
Further, the address signal BA outputted from the address counter is outputted in response to the burst control signal BS.
Accordingly, timing where a signal generated by decoding the address signal BA outputted from the address counter by the decoder circuit is supplied to the first latch circuit has a delay relative to the internal clock signal.